About Us メンバー

1991年(平3)東京大学工学部電子工学科卒業。93年(平5)同修士課程修了、96年(平8)同博士課程修了、工学博士。同年(株)東芝入社。2002年～2004年スタンフォード大学客員研究員。2011年まで(株)東芝半導体研究開発センターにて無線通信回路と低消費電力回路の研究開発に従事。2011年から2016年まで、(株)東芝ミックスドシグナルIC事業部にて、アナログミックスドシグナルICの製品開発を牽引。2016年、慶応義塾大学に移り、特任教授。2007年IEEE International Conference on Computer Design (ICCD) にてBest Paper Award、Design Automation Conference(DAC) 2010 にてBest User Track Poster Awardを受賞するとともに、ISSCC2013にて“AUTHORS of TEN OR MORE PAPERS IN THE PAST TEN YEARS”にリストされる。ISSCC技術プログラム委員(2003-2009,2011)、A-SSCC技術プログラム委員(2005-2012)。A-SSCCでは、RF/Digital/Student Design Contestの小委員会委員長およびプログラム委員会副委員長を歴任。

https://sites.google.com/view/atsutakekosuge/

http://www.dlab.t.u-tokyo.ac.jp/en/people/niwa.pdf

Dr. Kawano has been engaged in research and development of process and packaging technologies for three-dimensional stacked memory, FOWLP, and hybrid bonding at a major Japanese semiconductor manufacturer, a European equipment supplier, and a National Research Institute in Singapore. He has worked on international projects across Asia, the U.S., and Europe.

2007年東京理科大学専門職大学院総合科学研究科技術経営研究科(MOT)修了．1983年日本電気株式会社に入社．マイクロコンピュータ応用技術に従事．1993年から1998年IEEE802.3およびIEEE802.11標準化委員会で国際標準仕様を策定．1998年から2005年通信LSI研究開発、欧州向けカスタムIP開発に従事 (NEC エレクトロニクス株式会社)．2006年から2011年超低消費電力無線LSI開発に従事．2011年3月末にルネサスエレクトロニクス株式会社を退職． 2018年8月から2019年9月慶應義塾大学大学院理工学研究科研究員として非接触コネクタ応用研究に従事．2019年10月から東京大学大学院工学系研究科附属システムデザイン研究センターにて、システムデザインの研究開発に従事．IEEE 会員．

Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, and Mitsuji Okada, “An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs”, IEICE TRANS. FUNDAMENTALS, Vol. E98-A, No.12 Dec. 2015.

Mitsuji Okada, Yuzuru Shizuku and Tetsuya Hirose, “Circuit Design Techniques for Low Power Energy Harvesting System”, IEICE Technical Report, Vol.115, No.124, July 2-3 2015.

Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, and Mitsuji Okada, “Energy-Efficient AES SubBytes Transformation Circuit Using Asynchronous Circuits for Ultra-Low Voltage Operation”, IEICE Electronics Express, Letter, Vol.12, No.4, 2015

2013年1月31日 半導体理工学センター (STARC)『研究賞』 客員研究員主査 “Research on Fundamental Circuits for ultra-low power LSI systems utilized sub-threshold characteristics” with Kobe University

1981年3月慶應義塾大学工学部電気工学科卒業。1983年3月同大電気工学専攻修士課程修了。1983年4月現(株)東芝である東京芝浦電気(株)入社。音響事業部デジタルオーディオ開発部でCDプレーヤ用LSIの開発に従事。主に、レーザーピックアップサーボ技術を担当。'88年に世界初のデジタルサーボ搭載のCDプレーヤ用LSIを開発。1990年3月に半導体事業本部に転籍。1994年以降、CD/DVD/HDDVD用などの高倍速記録再生光ディスクシステムLSI開発に従事。HDDVD終息に伴い2009年からはミックスドシグナルIC事業部で、デジタル電源、モータードライバ、IoTセンサー用IC開発を担当。数々のアナデジLSIを開発。また、車載用ICの機能安全設計や東京工業大学と高速SARADC開発で産学連携にも従事。2019年9月に東芝を退職後、慶應義塾大学 黒田研究室で研究員として非接触コネクタの研究に従事。'20年4月から東大大学院システムデザイン研究センターで学術支援専門職員として勤務。

論文

• 外部記憶装置 読み出し線速度が可変の倍4速CD-ROMを開発（分担執筆) 1995年2月日経エレクトロニクス No.628
• システムLSI－アプリケーションと技術－(分担執筆) 1999年7月(株)サイエンスフォーラム

香港で生まれ育ち、大学からアメリカに在住。1988年にドイツのSiemens社にてインターンシップ。1990年米スタンフォード大学工学部電気工学科卒業、同年修士課程修了。アリゾナ州のMotorola Semiconductor Products Sector、南カリフォルニアのVitesse Semiconductor、シリコンバレーのLSI Logic、Sun Microelectronicsと Rambusを経て2014年に日本に移住東芝に入社。キャリアの前半は高速インタフェース・パッケージと基板の開発を担当、Sun UltraSPARC IIIプロセッサ・モジュールや、IntelメインメモリのRDRAMシステムや、ソニーPlayStation 3 CPUインターフェスなどの開発に従事。後半はアプリケーションエンジニアリング、事業開発、そしてテクニカルマーケッティングの役割を果たしながら技術の応用および普及に専念。東芝にて技術ライセンスと市場調査を担当。2018年10月より学術支援専門職員として黒田研究室に所属。

Inductive Coupling Inter-Chip Wireless Communication

High-speed I/O Interface

3D Integration

Efficient AI Architecture

Artificial Intelligence

Efficient AI inference processing chips will play an important role in next-generation edge computing, and memory will play a key role because AI inference processing operations require massively parallel memory accesses. In order to realize memory-centric low-cost and low-power AI hardware, I am researching on an efficient architecture using TSV-less 3D-stacked SRAM. Replacing TSV, the wired connection method found in stacked memory, with TCI (ThruChip Interface), a wireless connection method using on-chip coils, will simplify the manufacturing process and lower the cost. In addition, by replacing DRAM with 3D-stacked SRAM, a large-capacity memory with random access and low latency can be obtained, enabling low-power memory access that was not possible with conventional architectures.

Journal Papers

• [1] K. Shiba, M. Hamada, and T. Kuroda, "3D system-on-a-chip design with through-silicon-via-less power supply using highly doped silicon via," Japanese Journal of Applied Physics (JJAP), vol. 59, no. SG, pp. SGGL04, Apr. 2020.
• [2] K. Shiba, C. Cheng, M. Hamada, and T. Kuroda, "2.5D integration using inductive-coupling TSV-less miniature interposer achieving 317 Gb/s/mm², 1.2 pJ/b data-transfer," Japanese Journal of Applied Physics (JJAP), vol. 59, no. SG, pp. SGGL06, Apr. 2020.
• [3] K. Shiba, T. Omori, M. Usui, M. Hamada, and T. Kuroda, “Area-Efficient Multihop Inductive Coupling Interface for 3D-Stacked Memory With 0.23-V Transmitter and Sub-10-µm Coil Design,” IEEE Solid-State Circuits Letters (SSC-L), vol. 3, pp. 370-373, 2020.
• [4] K. Shiba, T. Omori, K. Ueyoshi, S. Takamaeda-Yamazaki, M. Motomura, M. Hamada, and T. Kuroda, “A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS,” IEEE Transactions on Circuits and Systems-I: Regular Papers (TCAS-I), vol. 68, no. 2, pp. 692-703, Feb. 2021.
• [5] R. Miura, S. Shibata, M.Usui, K. Shiba, A. Kosuge, M. Hamada and T. Kuroda, "A bonding-less 5-GHz RFID module using inductive coupling between IC and antenna," Japanese Journal of Applied Physics (JJAP), vol. 61, no. SC, pp. SC1058, Feb. 2022.

International Conference Papers

• [1] K. Shiba, M. Hamada, and T. Kuroda, "3D SoC Design with TSV-less Power Supply Employing Highly Doped Silicon Via," JSAP International Conference on Solid State Devices and Materials (SSDM'19), Extended Abstracts, pp. 515-516, Sep. 2019.
• [2] C. Cheng, K. Shiba, M. Hamada, and T. Kuroda, "2.5D Integration Using Inductive-Coupling TSV-less Miniature Interposer Achieving 317Gb/s/mm², 1.2pJ/b Data Transfer," JSAP International Conference on Solid State Devices and Materials (SSDM'19), Extended Abstracts, pp. 517-518, Sep. 2019.
• [3] K. Shiba, T. Omori, K. Ueyoshi, K. Ando, K. Hirose, S. Takamaeda-Yamazaki, M. Motomura, M. Hamada, and T. Kuroda, "A 3D-Stacked SRAM Using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes," IEEE International Symposium on Circuits and Systems (ISCAS2020), Oct. 2020.
• [4] M. Usui, K. Shiba, M. Hamada, and T. Kuroda,“3D Integration of Ka-band RFIC by Inductive Inter-chip Wireless Communication Using Figure-8 Coils,” IEEE 29th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Oct. 2020.
• [5] K. Ando, K. Shiba, K. Akatsuka, C. Cheng, T. Arakawa, M. Hamada, T. Kuroda, "A 50 Mbps/pin 12-input/output 40 nsec Latency Wireless Connector Using a Transmission Line Coupler with Compact SERDES IC in 180 nm CMOS," IEEE Conference on Electronics Circuits and Systems (ICECS), Nov. 2020.
• [6] K. Shiba, T. Omori, M. Okada, M. Hamada, and T. Kuroda, “Crosstalk Analysis and Countermeasures of High-Density Multi-Hop Inductive Coupling Interface for 3D-Stacked Memory,” IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), Dec. 2020.
• [7] K. Shiba, T. Omori, M. Hamada, and T. Kuroda, “A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS,” 26th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 97-98, Jan. 2021.
• [8] T. Omori, K. Shiba, M. Hamada, and T. Kuroda, “Sub-10-µm Coil Design for Multi-Hop Inductive Coupling Interface,” 26th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 99-100, Jan. 2021.
• [9] R. Miura, S. Shibata, M. Usui, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, "A Bonding-less 5-GHz RFID Module Using a 300um x 500um IC Chip," JSAP International Conference on Solid State Devices and Materials (SSDM'21), Extended Abstracts, pp. 686-687, Sep. 2021.
• [10] K. Shiba, T. Omori, M. Hamada, and T. Kuroda, “Area-Efficient Multi-Hop Inductive Coupling Interface for 3D-Stacked Memory with 0.23-V Transmitter and Sub-10-µm Coil Design,” IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2021.
• [11] S. Shibata, R. Miura, Y. Sawabe, K. Shiba, A. Kosuge, M. Hamada, T. Kuroda, "A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna," IEEE Asian Solid-State Circuits Conference (A-SSCC'21), Nov. 2021.
• [12] T. Omori, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, “A Physical Verification Methodology for 3D-ICs Using Inductive Coupling,” IEEE Electrical Design of Advanced Packaging and Systems(EDAPS), pp. 72-74, Dec. 2021.
• [13] K. Shiba, T. Omori, K. Ueyoshi, S. Takamaeda-Yamazaki, M. Motomura, M. Hamada, and T. Kuroda, “A 96-MB 3D-Stacked SRAM Using Inductive Coupling with 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2022.
• [14] K. Shiba, M. Okada, A. Kosuge, M. Hamada, and T. Kuroda, “Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format,” IEEE International New Circuits and Systems Conference (NEWCAS), June 2022.
• [15] Y.-C. Hsu, A. Kosuge, R. Sumikawa, K. Shiba, M. Hamada, and T. Kuroda, “A 13.7µJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA Using Non-Linear Neural Network,” IEEE Hot Chips 34 Symposium (HCS), Aug. 2022.
• [16] K. Shiba, M. Okada, A. Kosuge, M. Hamada, and T. Kuroda, “A 7-nm FinFET 1.2-TB/s/mm² 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers,” IEEE Hot Chips 34 Symposium (HCS), Aug. 2022.
• [17] K. Shiba, M. Okada, A. Kosuge, M. Hamada, and T. Kuroda, “A 12.8-Gbps 0.5-pJ/b Encoding-less Inductive Coupling Interface Using Clocked Hysteresis Comparator for 3D-Stacked SRAM in 7-nm FinFET,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2022.

Domestic Conference Papers

• [1] 柴康太, 宮田知輝, 門本淳一郎, 天野英晴, 黒田忠広, "ThruChip Interfaceの設計自動化," 情報処理学会 全国大会, Mar. 2018.

Lectures

• [1] 柴康太, 小菅敦丈, 濱田基嗣, 黒田忠広, “[招待講演] 三次元積層SRAMと近接場無線接続技術,” 電子情報通信学会(IEICE) 集積回路研究会(ICD) メモリ技術と集積回路技術一般, Apr. 2022.

Commentary

• [1] 柴康太, 小菅敦丈, 濱田基嗣, 黒田忠広, “近接場無線接続技術を用いた三次元積層SRAM,” エレクトロニクス実装学会誌, vol. 25, no. 6, pp. 549-555, Sep. 2022.

[1] 平成29年度 電気学術奨励賞, 電気学会東京支部, 2018年3月.

"Efficient Architecture of 3D-Stacked AI Chips," JST ACT-X

"TSV-less 3D-Stacked SRAM," JSPS DC2

http://kotashiba.com/

Domestic Conference Papers

• [1] 孟浩鵬, 若林一敏, 黒田忠広, "高位合成による浮動小数点用QR分解ハードウェアの設計," 情報処理学会 DAシンポジウム2021論文集, pp. 46-51, Aug. 2021.

International Conference Papers

• [1] H. Meng, K. Wakabayashi, and T. Kuroda, "A Scalable Linear Equation Solver FPGA using High-Level Synthesis," The 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2022), Oct. 2022.

Journal Papers

• [1] R. Miura, S. Shibata, M.Usui, K. Shiba, A. Kosuge, M. Hamada and T. Kuroda, "A bonding-less 5-GHz RFID module using inductive coupling between IC and antenna," Japanese Journal of Applied Physics (JJAP), vol. 61, no. SC, pp. SC1058, Feb. 2022.
• [2] S. Shibata, R. Miura, Y. Sawabe, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, "A 5-GHz 0.15-mm² Collision-Avoiding RFID Employing Complementary Pass-Transistor Adiabatic Logic With an Inductively Connected External Antenna in 0.18-μm CMOS,"IEEE Solid-State Circuits Letters (SSC-L), vol. 5, pp. 268-271, Nov. 2022.

International Conference Papers

• [1] R. Miura, S. Shibata, M. Usui, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, "A Bonding-less 5-GHz RFID Module Using a 300um x 500um IC Chip," JSAP International Conference on Solid State Devices and Materials (SSDM'21), Extended Abstracts, pp. 686-687, Sep. 2021.
• [2] S. Shibata, R. Miura, Y. Sawabe, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, "A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna," IEEE Asian Solid-State Circuits Conference (A-SSCC'21), Nov. 2021.
• [3] R. Miura, S. Shibata, M. Usui, A. Kosuge, M. Hamada, and T. Kuroda, “A 5.2GHz RFID Chip Contactlessly Mountable on FPC at Any 90-Degree Rotation and Face Orientation,” 27th Asia and South Pacific Design Automation Conference (ASP-DAC'22), pp. 5-6, Jan. 2022.
• [4] S. Shibata, R. Miura, Y. Sawabe, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, "A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna (invited)," IEEE 48th European Solid-State Circuits Conference (ESSCIRC 2022), Sep. 2022.
• [5] S. Shibata, Y. Sawabe, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, "A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic," 29th IEEE International Conference on Electronics Circuits and Systems(ICECS 2022), Oct. 2022.

Journal Papers

• [1] A. Kosuge, Y. -C. Hsu, M. Hamada, and T. Kuroda, "A 0.61-µJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using ConvolutionalNon-Linear Neural Network," Open Journal of Circuits and Systems (OJCAS), vol. 3, pp. 4-14, Jan. 2022.

International Conference Papers

• [1] Y.-C. Hsu, A. Kosuge, R. Sumikawa, K. Shiba, M. Hamada, and T. Kuroda, “A 13.7µJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA Using Non-Linear Neural Network,” IEEE Hot Chips 34 Symposium (HCS), Aug. 2022.

International Conference Papers

• [1] X. Wang, A. Kosuge, Y. Hayashi, M. Hamada, T. Kuroda, "A 12.5 Gb/s 1.1 pJ/b Rotatable Transmission Line Coupler Using Deep-Proximity Coupling Mode and Ground-Shield Vias," 2022年電子情報通信学会(IEICE)ソサイエティ大会, Sep. 2022.
• [2] X. Wang, A. Kosuge, Y. Hayashi, M. Hamada, T. Kuroda, "A 7 Gb/s Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shielding Vias," 29th IEEE International Conference on Electronics Circuits and Systems (ICECS 2022), Oct. 2022.

International Conference Papers

• [1] L. Yu, A. Kosuge, M. Hamada, T. Kuroda, "An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique,"2022 IEEE Sensors Applications Symposium (SAS), Aug. 2022.

Domestic Conference Papers

• [1] L. Yu, A. Kosuge, M. Hamada, T. Kuroda, "Polarized-Image Fusion Based Anomaly Detection System for Food Industry Applications," The 25th Meeting on Image Recognition and Understanding, July 2022.

Domestic Conference Papers

• [1] 小林英太郎, 小菅敦丈, 末廣知士, 濱田基嗣, 黒田忠広, "mmWave-YOLOによるミリ波レーダを用いたリアルタイム多クラス物体認識," 第25回 画像の認識･理解シンポジウム, July 2022.

International Conference Papers

• [1] R. Sumikawa, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, "A 1.2nJ/Classification 2.4mm2 Wired-Logic Neuron Cell Array Using Logically Compressed Non-Linear Function Blocks in 0.18um CMOS," JSAP International Conference on Solid State Devices and Materials (SSDM'22), Extended Abstracts, pp. 750-751, Sep. 2022.