Publication 発表


8 T. Kuroda,
"CMOS design challenges to power wall (plenary),"
International Microprocesses and Nanotechnology Conference, Dig. Tech. Papers, pp. 6-7, Oct. 2001.
7 T. Kuroda,
International Conference on Solid State Devices and Materials (SSDM’01) Short Course B, Sep. 2001.
6 T. Kuroda,
"Low power CMOS design challenges,"
IEICE Trans. Electronics, vol. E84-C, no. 8, pp. 1021-1028, Aug. 2001.
5 黒田忠広,
電子情報通信学会誌, vol. 84, no. 8 pp. 552-558, Aug. 2001.
4 T. Kuroda,
"2001 IEEE Symposium on VLSI Circuits Report,"
Electronic Journal, pp. 86-87, Jul. 2001.
3 T. Kuroda,
"2001 CICC Report,"
Electronic Journal, pp. 86-87, Jul. 2001.
2 K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda,
"A bit-line leakage compensation scheme for low-voltage SRAM’s,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 36, no. 5, May 2001.
1 M. Hamada, Y. Ootaguro, and T. Kuroda,
"Utilizing surplus timing for power reduction,"
in Proc. IEEE Custom Integrated Circuits Conference (CICC’01), pp. 89-92, May 2001.