|8||K. Shiba, M. Okada, A. Kosuge, M. Hamada, T. Kuroda,
"Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS,"
IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 9, pp. 3440-3450, Sep. 2023.
|7||K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda,
"Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface,"
IEICE Transactions on Electronics, vol. E106-C, no. 7, pp. 391-394, July 2023.
|6||K. Shiba, M. Okada, A. Kosuge, M. Hamada, and T. Kuroda,
"A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 58, no. 7, pp. 2075-2086, July 2023.
|5||X. Wang, A. Kosuge, Y. Hayashi, K. Shiba, M. Hamada, and T. Kuroda,
"Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application,"
IEEE International New Circuits and Systems Conference (NEWCAS), June 2023.
|4||A. Kosuge, L. Yu, M.Hamada, K. Matsuo, and T. Kuroda,
"A Deep Metric Learning-Based Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion,"
IEEE Open Journal of the Industrial Electronics Society, vol. 4, pp. 205-213, June 2023.
|3||A. Kosuge, R. Sumikawa, Y. -C. Hsu, K. Shiba, M. Hamada, and T. Kuroda,
"A 183.4nJ/inference 152.8uW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application,"
IEEE Symposium on VLSI Circuits, June 2023.
|2||N. Shimamoto, A. Mizushima, D. Bourrier, E. Ota, A. Higo, H. Granier, A. Kosuge, M. Ikeda, T. Kuroda, and Y. Mita,
"Micron-to-Submicron Cu electroplating in view of Agile-X LSI Chips Fabrication using Open Facility,"
The 3rd European Symposium on Nanofabrication Research Infrastructure(ENRIS 2023),May 2023.
|1||D. Li, Y. Hsu, R. Sumikawa, A. Kosuge, M. Hamada, and T. Kuroda,
"A 0.13mJ/Prediction CIFAR-100 Raster-Scan-Based Wired-Logic Processor Using Non-Linear Neural Network,"
IEEE International Symposium on Circuits and Systems (ISCAS), May 2023.