Papers(2012年度)
| 30 | T. Takeya, L. Nan, S. Nakano, N. Miura, H. Ishikuro, and T. Kuroda, "A 12-Gb/s non-contact interface with coupled transmission lines," IEEE Journal of Solid-State Circuits (JSSC), vol. 48, no. 3, pp. 790-800, Mar. 2013. |
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| 29 | T. Takeya, and T. Kuroda, "Symbol-Rate Clock Recovery for Integrating DFE Receivers," IEICE Trans. on Fundamentals, vol. E96-A, no. 3, pp. 705-712, Mar. 2013. |
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| 28 | A. Shikata, R. Sekimoto, K. Yoshioka, T. Kuroda, and H. Ishikuro, "A 4-10bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS with Wide Supply Voltage Range SAR Controller," IEICE Trans. on Fundamentals, vol. E96-A, no. 2, Feb. 2013. |
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| 27 | W. Mizuhara, T. Shidei, A. Kosuge, T. Takeya, N. Miura, M. Taguchi, H. Ishikuro, and T. Kuroda, "A 0.15mm-Thick Non-Contact Connector for MIPI Using Vertical Directional Coupler," IEEE International Solid-State Circuits Conference (ISSCC'13), Dig. Tech. Papers, pp. 200-201, Feb. 2013. |
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| 26 | H. Fukuda, T. Terada, and T. Kuroda, "Retrodirective Transponder Array with Universal On-Sheet Reference for Wireless Mobile Sensor Networks Without Battery or Oscillator," IEEE International Solid-State Circuits Conference (ISSCC'13), Dig. Tech. Papers, pp. 204-205, Feb. 2013. |
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| 25 | N. Miura, M. Saito, M. Taguchi, and T. Kuroda, "A 6nW Inductive-Coupling Wake-Up Transceiver for Reducing Standby Power of Non-Contact Memory Card by 500x," IEEE International Solid-State Circuits Conference (ISSCC'13), Dig. Tech. Papers, pp. 214-215, Feb. 2013. |
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| 24 | Y. Take, N. Miura, H. Ishikuro, and T. Kuroda, "3D Clock Distribution Using Vertically/Horizontally Coupled Resonators," IEEE International Solid-State Circuits Conference (ISSCC'13), Dig. Tech. Papers, pp. 258-259, Feb. 2013. |
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| 23 | H. Matsutani, P. Bogdan, R. Marculescu, Y. Take, D. Sasaki, H. Zhang, M. Koibuchi, T. Kuroda, and H. Amano, "A Case for Wireless 3D NoCs for CMPs," 18th Asia and South Pacific Design Automation Conference (ASP-DAC'13), Proceedings, pp. 23-28, Jan. 2013. |
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| 22 | K. Yoshioka, A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, "A 0.35-0.8V 8b 0.5-35MS/s 2bit/step Extremely-low Power SAR ADC," 18th Asia and South Pacific Design Automation Conference (ASP-DAC'13), Proceedings, pp. 111-112, Jan. 2013. |
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| 21 | A. Kosuge, W. Mizuhara, N. Miura, M. Taguchi, H. Ishikuro, and T. Kuroda, "A 12.5Gb/s/Link Non-Contact Multi-Drop Bus System with Impedance-Matched Transmission Line Couplers and Dicode Partial-Response Channel Transceivers," 18th Asia and South Pacific Design Automation Conference (ASP-DAC'13), Proceedings, pp. 91-92, Jan. 2013. |
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| 20 | Y. Koizumi, H. Amano, H. Matsutani, N. Miura, T. Kuroda, R. Sakamoto, M. Namiki, K. Usami, M. Kondo, and H. Nakamura, "Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect," International Conference on Field-Programmable Technology (ICFPT'12), pp. 293-296, Dec 2012. |
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| 19 | K. Tomita, R. Shinoda, T. Kuroda, and H. Ishikuro, "1-W 3.3–16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller," IEEE Journal of Solid-State Circuits (JSSC), vol. 47, no. 11, pp. 2576-2585, Nov. 2012. |
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| 18 | R. Sekimoto, A. Shikata, K. Yoshioka, T. Kuroda, and H. Ishikuro, "A 40nm CMOS Full Asynchronous Nano-Watt SAR ADC with 98% Leakage Power Reduction by Boosted Self Power Gating," IEEE Asian Solid-State Circuits Conference (A-SSCC'12), Proc. Tech. Papers, pp. 161-164, Nov. 2012. |
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| 17 | Y. Hiraku, I. Hayashi, H. Chung, T. Kuroda, and H. Ishikuro, "A 0.5V 10MHz-to-100MHz 0.47µW/MHz Power Scalable Ad-PLL in 40nm CMOS," IEEE Asian Solid-State Circuits Conference (A-SSCC'12), Proc. Tech. Papers, pp. 33-36, Nov. 2012. |
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| 16 | T. Kuroda, "ThruChip interface for heterogeneous chip stacking," ECS Transactions, vol. 14, no. 50, pp. 63-68, Oct. 2012. |
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| 15 | H. Chung, A. Radecki, N. Miura, H. Ishikuro, and T. Kuroda, "A 0.025–0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards," IEEE Journal of Solid-State Circuits (JSSC), vol. 47, no. 10, pp. 2496-2504, Oct. 2012. |
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| 14 | M. Saito, N. Miura, and T. Kuroda, "Analysis and Design of Coil with Feed Line for ThruChip Interface," JSAP International Conference on Solid State Devices and Materials (SSDM'12), Extended Abstracts, pp. 1160-1161, Sep. 2012. |
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| 13 | A. Kosuge, T. Takeya, M. Shioya, M. Taguchi, and T. Kuroda, "A 3Gb/s Non-Contact Inter-Module Link with Duplex Transmission-Line-Couplers and Low-Frequency Compensation Equalizer," JSAP International Conference on Solid State Devices and Materials (SSDM'12), Extended Abstracts, pp. 1152-1153, Sep. 2012. |
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| 12 | A. Kosuge, W. Mizuhara, N. Miura, M. Taguchi, H. Ishikuro, and T. Kuroda, "A 12.5Gb/s/Link Non-Contact Multi Drop Bus System with Impedance-Matched Transmission Line Couplers and Dicode Partial-Response Channel Transceivers," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), pp. 7.9.1-7.9.4, Sep. 2012. |
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| 11 | L. Liu, H. Ishikuro, and T. Kuroda, "A 100Mb/s 13.7pJ/bit DC-960MHz Band Plesiochronous IR-UWB Receiver with Costas-Loop Based Synchronization Scheme in 65nm CMOS," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), pp. 8.6.1-8.6.4, Sep. 2012. |
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| 10 | X. Zhu, Y. Chen, S. Tsukamoto and T. Kuroda, "A 9-bit 100MS/s SARADC with Digitally Assisted Background Calibration," IEICE Trans. on Electronics, vol. E95-C, no. 6, pp. 1026 -1034, June 2012. |
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| 9 | N. Miura, M. Saito, and T. Kuroda, "A 1TB/s 1pJ/b 6.4mm2/TB/s QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 2, no. 2, pp.249-256, June 2012. |
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| 8 | 黒田忠広, "近接場ワイヤレス通信が拓く三次元実装," エレクトロニクス実装学会誌, vol. 15, no. 4, pp. 231-235, May 2012. |
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| 7 | T. Kuroda, "Near-Field Wireless Connection for 3D-System Integration," IEEE Symposium on VLSI Technology, Dig. Tech. Papers, pp. 105-106, June 2012. |
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| 6 | Y. Shimazaki, N. Miura, and T. Kuroda, "A 5.184Gbps/ch Through-Chip Interface and Automated Place-and-Route Design Methodology for 3-D Integration of 45nm CMOS Processors," IEEE Symposium on low-Power and High-Speed Chips (COOL Chips) XV, Apr. 2012. |
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| 5 | H. Chung, H. Ishikuro, and T. Kuroda, "A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS," IEEE Journal of Solid-State Circuits (JSSC), vol. 47, no. 5, pp. 1232-1241, May. 2012. |
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| 4 | X. Zhu, Y. Chen, S. Tsukamoto, T. Kuroda, " A 9-bit 100MS/s Tri-level Charge Redistribution SAR ADC with Asymmetric CDAC Array," 2012 International Symposium on VLSI Design, Automation and Test (2012 VLSI-DAT), Hsinchu, Taiwan, Apr. 2012. |
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| 3 | M. Saito, N. Miura, and T. Kuroda, "Asynchronous Pulse Transmitter for Power Reduction in Inductive-Coupling Link," Japanese Journal of Applied Physics(JJAP), vol. 51 No. 2, Apr. 2012. |
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| 2 | A. Radecki, H.Chung, Y. Yoshida, N. Miura, T. Shidei, H. Ishikuro and T. Kuroda, "6W/25mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing," IEICE Trans. on Electronics, vol. E95-C, No. 4, pp. 668-676, Apr. 2012. |
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| 1 | A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, "A 0.5 V 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS," IEEE Journal of Solid-State Circuits (JSSC), vol. 47, no. 4, pp. 1022-1030, Apr. 2012. |
